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#ifndef __INCmvCtrlEnvLibh
#define __INCmvCtrlEnvLibh

/* includes */
#include "mvSysHwConfig.h"
#include "mvCommon.h"
#include "mvTypes.h"
#include "mvOs.h"
#include "ctrlEnv/mvCtrlEnvSpec.h"
#include "ctrlEnv/mvCtrlEnvRegs.h"
#include "ctrlEnv/mvCtrlEnvAddrDec.h"
/*#include "boardEnv/mvBoardEnvLib.h"*/

/* 0 for Auto scan mode, 1 for manual. */
#define MV_INTERNAL_SWITCH_SMI_SCAN_MODE	0

/* typedefs */
typedef MV_STATUS(*MV_WIN_GET_FUNC_PTR)(MV_U32, MV_U32, MV_UNIT_WIN_INFO*);

/* This enumerator describes the possible HW cache coherency policies the   */
/* controllers supports.                                                    */
typedef enum _mvCachePolicy {
    NO_COHERENCY,   /* No HW cache coherency support                        */
    WT_COHERENCY,   /* HW cache coherency supported in Write Through policy */
    WB_COHERENCY    /* HW cache coherency supported in Write Back policy    */
} MV_CACHE_POLICY;


/* The swapping is referred to a 64-bit words (as this is the controller    */
/* internal data path width). This enumerator describes the possible        */
/* data swap types. Below is an example of the data 0x0011223344556677      */
typedef enum _mvSwapType {
    MV_BYTE_SWAP,       /* Byte Swap                77 66 55 44 33 22 11 00 */
    MV_NO_SWAP,         /* No swapping              00 11 22 33 44 55 66 77 */
    MV_BYTE_WORD_SWAP,  /* Both byte and word swap  33 22 11 00 77 66 55 44 */
    MV_WORD_SWAP,       /* Word swap                44 55 66 77 00 11 22 33 */
    SWAP_TYPE_MAX	/* Delimiter for this enumerator                    */
} MV_SWAP_TYPE;

typedef enum {
	SERDES_UNIT_UNCONNECTED	= 0x0,
	SERDES_UNIT_PEX		= 0x1,
	SERDES_UNIT_SATA	= 0x2,
	SERDES_UNIT_SGMII0	= 0x3,
	SERDES_UNIT_SGMII1	= 0x4,
	SERDES_UNIT_SGMII2	= 0x5,
	SERDES_UNIT_SGMII3	= 0x6,
	SERDES_UNIT_QSGMII	= 0x7,
	SERDES_UNIT_LAST
} MV_SERDES_UNIT_INDX;

typedef enum {
	PEX_BUS_DISABLED	= 0,
	PEX_BUS_MODE_X1		= 1,
	PEX_BUS_MODE_X4		= 2,
	PEX_BUS_MODE_X8		= 3
} MV_PEX_UNIT_CFG;

/* Configuration per SERDES line.
   Each nibble is MV_SERDES_LINE_TYPE */
typedef struct _boardSerdesConf {
	MV_U32 enableSerdesConfiguration; /*This will determine if mvCtrlSerdesPhyConfig will configure the serdes*/
	MV_U32	serdesLine0_7;	/* Lines 0 to 7 SERDES MUX one nibble per line */
	MV_U32	serdesLine8_15;	/* Lines 8 to 15 SERDES MUX one nibble per line */
	MV_PEX_UNIT_CFG		pex0Mod;
	MV_PEX_UNIT_CFG		pex1Mod;
	MV_PEX_UNIT_CFG		pex2Mod;
	MV_PEX_UNIT_CFG		pex3Mod;
	MV_U32	busSpeed;	/* Bus speed - one bit per SERDES line:
	Low speed (0)		High speed (1)
	PEX	2.5 G (10 bit)		5 G (20 bit)
	SATA	1.5 G			3 G
	SGMII 	1.25 Gbps		3.125 Gbps	*/
} MV_SERDES_CFG;
/* Termal Sensor Registers */
#define TSEN_STATUS_REG					0x182B0
#define	TSEN_STATUS_TEMP_OUT_OFFSET		19
#define	TSEN_STATUS_TEMP_OUT_MASK		(0x1FF << TSEN_STATUS_TEMP_OUT_OFFSET)

#define TSEN_CONF_REG					0x184D0
#define	TSEN_CONF_OTF_CALIB_MASK		(0x1 << 30)
#define	TSEN_CONF_REF_CAL_MASK			(0x1FF << 11)
#define	TSEN_CONF_SOFT_RESET_MASK		(0x1 << 1)
#define	TSEN_CONF_START_CALIB_MASK		(0x1 << 25)


/* BIOS Modes related defines */
#define SAR0_CPU_FREQ_MASK	0x00E00000
#define SAR0_CPU_FREQ_OFFSET	21
#define SAR0_FABRIC_FREQ_MASK	0x0F000000
#define SAR0_FABRIC_FREQ_OFFSET	24
#define SAR0_L2_SIZE_MASK	0x00180000
#define SAR0_L2_SIZE_OFFSET	19
#define SAR0_BOOTSRC_MASK	0X1E0
#define SAR0_BOOTSRC_OFFSET	5
#define SAR0_BOOTWIDTH_MASK	0X18
#define SAR0_BOOTWIDTH_OFFSET	3
#define SAR0_CPU0CORE_MASK	0X80000000
#define SAR0_CPU0CORE_OFFSET	31
#define PEX_CLK_100MHZ_MASK    0x00000004
#define PEX_CLK_100MHZ_OFFSET  2
#define SAR1_CPU0CORE_MASK	0x1
#define SAR1_CPU0CORE_OFFSET	0
#define SAR1_CPU_CORE_MASK	0x00000018
#define SAR1_CPU_CORE_OFFSET	3
#define SAR1_CPU_MODE_MASK	0x00100000
#define SAR1_CPU_MODE_OFFSET	20
#define SAR1_FABRIC_MODE_MASK	0x00080000
#define SAR1_FABRIC_MODE_OFFSET	19

#define SAR_CPU_FAB_GET(cpu, fab)	(((cpu & 0x7) << 21) | ((fab & 0xF) << 24))
#ifdef MV88F78X60_Z1
#define BIOS_MODES_NUM			7
#else
#define BIOS_MODES_NUM			6
#endif


typedef struct {
	char *name;
	MV_U16 confId;
	MV_U16 code;
	MV_U8 l2size;
	MV_U8 cpuFreq;
	MV_U8 cpuFreqMode;
	MV_U8 fabricFreq;
	MV_U8 AltfabricFreq;
	MV_U8 fabricFreqMode;
	MV_U8 cpuEna;
#ifdef MV88F78X60_Z1
	MV_U8 cpuMode;
#else
	MV_U8 cpuEndianess;
#endif
	MV_U8 dramBusWidth;
	MV_U8 bootSource;
	MV_U8 bootWidth;	
} MV_BIOS_MODE;

extern MV_BIOS_MODE bios_modes[];

/* mcspLib.h API list */
MV_U32 mvCtrlGetCpuNum(MV_VOID);
MV_U32 mvCtrlGetQuadNum(MV_VOID);
MV_STATUS mvCtrlUpdatePexId(MV_VOID);

MV_STATUS mvCtrlEnvInit(MV_VOID);
MV_U32    mvCtrlMppRegGet(MV_U32 mppGroup);

#if defined(MV_INCLUDE_PEX)
MV_U32	mvCtrlPexMaxIfGet(MV_VOID);
MV_U32	mvCtrlPexMaxUnitGet(MV_VOID);
#else
#define mvCtrlPexMaxIfGet()	(0)
#endif

#if defined(MV_INCLUDE_PCI)
MV_U32	mvCtrlPciMaxIfGet(MV_VOID);
#else
#define mvCtrlPciIfMaxIfGet()	(mvCtrlPexMaxIfGet())
#endif

MV_U32	  mvCtrlEthMaxPortGet(MV_VOID);
MV_U8	  mvCtrlEthMaxCPUsGet(MV_VOID);
#if defined(MV_INCLUDE_XOR)
MV_U32 mvCtrlXorMaxChanGet(MV_VOID);
MV_U32 mvCtrlXorMaxUnitGet(MV_VOID);
#endif
#if defined(MV_INCLUDE_USB)
MV_U32 	  mvCtrlUsbMaxGet(MV_VOID);
#endif
#if defined(MV_INCLUDE_LEGACY_NAND)
MV_U32	  mvCtrlNandSupport(MV_VOID);
#endif
#if defined(MV_INCLUDE_SDIO)
MV_U32	  mvCtrlSdioSupport(MV_VOID);
#endif
#if defined(MV_INCLUDE_TDM)
MV_U32	  mvCtrlTdmSupport(MV_VOID);
MV_U32	  mvCtrlTdmMaxGet(MV_VOID);
MV_UNIT_ID mvCtrlTdmUnitTypeGet(MV_VOID);
MV_U32    mvCtrlTdmUnitIrqGet(MV_VOID);
#endif

MV_U16    mvCtrlModelGet(MV_VOID);
MV_U8     mvCtrlRevGet(MV_VOID);
MV_STATUS mvCtrlNameGet(char *pNameBuff);
MV_U32    mvCtrlModelRevGet(MV_VOID);
MV_STATUS mvCtrlModelRevNameGet(char *pNameBuff);
MV_VOID   mvCtrlAddrDecShow(MV_VOID);
const MV_8 *mvCtrlTargetNameGet(MV_TARGET target);
MV_U32	  ctrlSizeToReg(MV_U32 size, MV_U32 alignment);
MV_U32	  ctrlRegToSize(MV_U32 regSize, MV_U32 alignment);
MV_U32	  ctrlSizeRegRoundUp(MV_U32 size, MV_U32 alignment);
MV_U32	  mvCtrlSysRstLengthCounterGet(MV_VOID);
MV_STATUS ctrlWinOverlapTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2);
MV_STATUS ctrlWinWithinWinTest(MV_ADDR_WIN *pAddrWin1, MV_ADDR_WIN *pAddrWin2);

MV_VOID   mvCtrlPwrClckSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable);
MV_BOOL	  mvCtrlPwrClckGet(MV_UNIT_ID unitId, MV_U32 index);
MV_VOID   mvCtrlPwrMemSet(MV_UNIT_ID unitId, MV_U32 index, MV_BOOL enable);
MV_BOOL	  mvCtrlIsBootFromNOR(MV_VOID);
MV_BOOL	  mvCtrlIsBootFromSPI(MV_VOID);
MV_BOOL	  mvCtrlIsBootFromNAND(MV_VOID);
MV_BOOL	  mvCtrlPwrMemGet(MV_UNIT_ID unitId, MV_U32 index);

MV_U32 mvCtrlSerdesMaxLinesGet(MV_VOID);
MV_STATUS mvCtrlSerdesPhyConfig(MV_VOID);
MV_U32 mvCtrlDDRBudWidth(MV_VOID);
MV_BOOL mvCtrlDDRThruXbar(MV_VOID);
MV_BOOL mvCtrlDDRECC(MV_VOID);

#endif /* __INCmvCtrlEnvLibh */
